1. Field of the Invention
The invention relates to the field of memory systems which include a plurality of memory "chips", particularly memory systems employing "mostly good" memory chips.
2. Prior Art
During the fabrication of memory chips, many such memories are formed which are "mostly good". That is, memories are fabricated having only a few faulty elements such as a faulty cell, line, decoder, etc. Typically in the fabrication of MOS memories, most defective memories (chips) have fewer than 10 bad elements. When memory chips are fabricated with redundant elements, more "perfect" memories result when redundant elements are used. However, the redundancy also provides more mostly good memories. For example, if a memory has 3 defective rows, and there are four redundant rows that may be used to replace the defective rows, a perfect memory results, at least from the user's standpoint. If another memory has six defective rows, the use of the four redundant rows only results in a mostly good memory.
It has been the practice in the semiconductor industry to use mostly good memories for fabricating memory systems. In one scheme, the mostly good memories are sorted into memories having 1/4, 1/2 or 3/4 usable memory capacity which falls into predetermined address ranges. Then, by way of example, a memory system is fabricated using memories with 1/2 usable capacity where the usable capacity falls within the same address range. Obviously, with this scheme, it is necessary to stock a large number of different mostly good memories. Moreover, many mostly good memories cannot be used with this sorting scheme since the usable capacity may not fall within predetermined address ranges. The above described sorting does not provide good utilization of mostly good memories. For example, a memory having three defective elements could be classified as only having 1/4 usable capacity, depending upon the addresses at which the defective elements are located. A single defective element could cause a mostly good memory to be classified as having only 1/2 usable capacity again depending on the location of the defective element. As will be seen, the present invention greatly reduces the sorting problems described above, and more importantly, permits much better utilization of the usable capacity of mostly good memories. In general, with the present invention, a redundant memory chip is used with addressing means which cause selection of the redundant memory when an address is received by the memory system corresponding to a defective element in a mostly good memory.
Applicant has conducted a search; the following patents were uncovered during the search:
______________________________________ U.S. Pat. No. Patentee Issue Year ______________________________________ 3,350,690 Rice 1967 3,772,652 Hilberg 1973 3,803,560 DeVoy et al 1974 3,995,261 Goldberg 1976 3,999,051 Petschauer 1976 4,051,354 Choate 1977 4,051,460 Yamada et al 1977 4,066,880 Salley 1978 4,092,733 Cootnz, et al 1978 ______________________________________